The present invention relates to implementing Memory Built-In Self Test (MBIST) architectures, and more particularly to a data structure that can be inputted into a design tool for describing a specific arrangement of an MBIST architecture.
Integrated circuit (IC) chips are typically designed within a software platform, e.g., using a register transfer language (RTL) tool. Along with laying out the functional components of the chip, an MBIST architecture arrangement must also be incorporated into the design to provide Design For Test (DFT) capabilities. As chip designs become increasingly more complex, MBIST architectures likewise need to evolve.
The MBIST architectural arrangement may often be driven by the needs of a particular customer. For instance, a customer may define which memories will share a given MBIST engine. For system test partitioning, especially related to the use of voltage islands, the customer may decide to partition the embedded memories into multiple MBIST partitions, in which case they must also define which memories will belong to each memory BIST partition. The customer may also decide, in the case of multiple voltage islands, to divide the memories into multiple fuse partitions.
It is, therefore, becoming increasingly more important to offer methods to help a customer streamline the DFT insertion of MBIST blocks into a design to provide the customer's desired MBIST architectural arrangement.